Data: Lateral tunnel epitaxy of GaAs in lithographically defined cavities on 220 nm silicon-on-insulator

Current heterogeneous Si photonics usually bond III-V wafers/dies on silicon-on-insulator (SOI) substrate in a back-end process, whereas monolithic integration by direct epitaxy could benefit from a front-end process where III-V materials are grown prior to the fabrication of passive optical circuits. Here we demonstrate a front-end-of-line (FEOL) processing and epitaxy approach on Si photonics 220 nm (001) SOI wafers, to enable positioning dislocation-free GaAs layers in lithographically defined cavities right on top of the buried oxide layer. Thanks to the defect confinement in lateral growth, threading dislocations generated from the III-V/Si interface are effectively trapped within ~250 nm from the Si surface. This demonstrates the potential of in-plane co-integration of III-Vs with Si on mainstream 220 nm SOI platform without relying on thick, defective buffer layers.

• The dataset includes PL scans taken with a 40uW 660nm pumping laser corresponding to Fig. 7 in the publication. The data is contained in separate .txt files separated in two columns: wavelength in nm and PL intensity in a.u.. The file names indicate the laser power after the attenuator in percents and the exposure time in seconds.
  

Research results based upon these data are published at https://doi.org/10.1021/acs.cgd.3c00633